The present invention relates to techniques effectively applied to embedded wiring technology in a manufacturing method for a semiconductor integrated circuit device (or a semiconductor device).
Japanese Unexamined Patent Publication No. 2007-150359 (Patent Document 1) discloses that an atmosphere in an integrated chemical mechanical polishing (CMP) and cleaning device is transformed to inert gas in a copper damascene interconnect process.
Japanese Unexamined Patent Publication No. 2001-148385 (Patent Document 2) or U.S. Pat. No. 6,897,150 (Patent Document 3) discloses that a corrosion prevention process using a benzo-tri-azole (BTA) is applied in cleaning after the CMP process of the copper damascene interconnect process.
Japanese Unexamined Patent Application Publication (Translation of a PCT application) No. 2007-511894 (Patent Document 4) or U.S. Pat. No. 7,188,630 (Patent Document 5) discloses that a cleaning solution containing an antiseptic agent is used for cleaning after the CMP processing of the copper damascene interconnect process.    [Patent Document 1] Japanese Unexamined Patent Publication No. 2007-150359    [Patent Document 2] Japanese Unexamined Patent Publication No. 2001-148385    [Patent Document 3] U.S. Pat. No. 6,897,150    [Patent Document 4] Japanese Unexamined Patent Application Publication (Translation of a PCT application) No. 2007-511894    [Patent Document 5] U.S. Pat. No. 7,188,630